1. Field of the Invention
This invention pertains to a symmetrical analog power amplifier, and more particularly to an analog power amplifier which includes an output stage that has a pull up/pull down arrangement to provide improved performance characteristics. The amplifier also includes a power down circuit to reduce power consumption. The symmetrical analog power amplifier of this invention is designed to be used in a variety of applications including computer network cards, as well as other devices.
2. Description of the Related Art
Power amplifiers have high power output stages and are widely used as voltage reference signal buffers and for providing circuit isolation. Such amplifiers have high input impedance and low output impedance. Having low output impedance enables the amplifier to deliver the output signal to a large load without significant distortion.
A conventional power amplifier in the form of a two-stage op amp is shown on the attached FIG. 1. The amplifier uses a p-input stage, which generates less 1/f noise, has a higher slew rate and has a more favorable input range than an n-input stage. This amplifier is used when the input signal is not too high (i.e., between VSS and VDD--0.7).
The first stage of the conventional amplifier is a differential input stage comprising a pair of PMOS input transistors Q1 and Q2 which are actively loaded with a pair of NMOS transistors that are connected in current mirror configuration. A PMOS current source transistor Q5, controlled by a bias voltage V.sub.bias1 which is applied to the gate of Q5, supplies current to each of the input transistors Q1 and Q2. The input stage produces a single ended output voltage V.sub.out1 at the node defined by the drain-drain connection between Q2 and Q4. This node where V.sub.out1 is generated interconnects the input stage with a compensation network of the second stage which is an output stage. The compensation network, which includes transistor Q16 and capacitor Cc, is connected between the node where V.sub.out1 is produced and the output node where V.sub.out2 is generated. The output stage includes a current amplifier transistor Q7 that is actively loaded with a PMOS current source transistor Q6. Q6 and Q7 are controlled by V.sub.bias1 and V.sub.out1 respectively. V.sub.out2 is taken off of the node formed by the drain--drain connection between Q6 and Q7.
In operation, the current through Q7 changes as V.sub.out1 and V.sub.out2 change. With the compensation components Q16 and Cc, the amplifier provides a relatively stable output. However, one disadvantage to this design is that the pull up current available for charging the load is limited by Q6 which limits the current therethrough to a relatively small amount (i.e., 0.5 mA). The amplifier's weak pull up capability coupled with its strong pull down capability (that is, its ability to discharge current from the load) results in an asymmetric output signal and large distortion. Another disadvantage to this design is that the amplifier lacks the capability to reduce power consumption when it is in an idle state (i.e., when no input signal is applied) because it has a large cross current in the idle state.